FIG. 1 shows a known IGBT with planar gate electrodes. The IGBT is a device with a four-layer structure, which are arranged between an emitter electrode 2 on an emitter side 11 and a collector electrode 25 on a collector side 15, which is arranged opposite of the emitter side 11. An (n-) doped drift layer 6 is arranged between the emitter side 11 and the collector side 15. A p doped planar base layer 405 is arranged between the drift layer 6 and the emitter electrode 2, which planar base layer 405 is in direct electrical contact to the emitter electrode 2. A planar n-doped source region 505 is arranged on the emitter side 11 embedded into the planar base layer 405 and contacts the emitter electrode 2.
A planar gate electrode 305 is arranged on top of the emitter side 11. The planar gate electrode 305 is electrically insulated from the planar base layer 405, the planar source region 505 and the drift layer 6 by a planar insulating layer 306. There is a further insulating layer 309 arranged between the planar gate electrode 305 and the emitter electrode 2.
The terms “planar” or “trench” base layer and “planar” or “trench” source region can be considered to distinguish the layers from each other for the different device types, not to imply any special design or any further technical meaning.
Such a planar MOS cell design can exhibit various characteristics when applied to BiMOS type switch concepts. The device can have high on-state losses due to a plurality of effects. The planar design offers a lateral MOS channel which can incur charge spreading (also called JFET effect) near the cell. Therefore the planar cells show low carrier enhancement. Furthermore, due to the lateral channel design, the planar design can incur hole drain effect (PNP effect) due to the bad electron spreading out of the MOS channel. The region between the cells offers strong charge enhancement for the PiN diode part. This PiN effect, however, can only show a positive impact in high voltage devices with low cell packing densities (a low number of cells in an area). In order to achieve reduced channel resistance the planar devices are made with less cell packing density, and this can only be compensated with narrow pitches (distance between two cells), thereby reducing the PiN effect.
Concerning the blocking capability the planar design can provide good blocking capability due to low peak fields at the cells and between the cells.
The planar design can have a large MOS accumulation region below the gate electrode and large associated capacitance. Nevertheless, the device can show good controllability due to the application of a field oxide type layer between the cells for miller capacitance reduction. Therefore, good controllability and low switching losses can be achieved for planar design.
Furthermore, the cell densities in planar designs can be easily adjusted for the required short circuit currents.
As a result taking all above mentioned effects into account, known planar cells apply very narrow cells and wide pitches with Field Oxide layers.
Alternatively to planar designs, trench MOS cell designs as shown in FIG. 2 have been introduced, in which a trench gate electrode 300 is electrically insulated from a trench base layer 400, a trench source region 500 and the drift layer 6 by a trench insulating layer 301. The trench gate electrode 300 is arranged in the same plane and lateral to the trench base layer 400 and extends deeper into the drift layer 6 than the trench base layer 400.
With such trench gate electrode designs, the on-state losses are lower, because the trench design offers a vertical MOS channel, which provides enhanced injection of electrons in the vertical direction and incurs no drawbacks from charge spreading (so called JFET effect) near the cell. Therefore the trench cells can possess improved carrier enhancement for lower losses. Due to the vertical channel design, the trench offers also less hole drain effect (PNP effect) due to improved electron spreading out of the MOS channel. At the bottom of the trench there is an accumulation layer, which offers strong charge enhancement for the PIN diode part. Hence wide and/or deep trenches can optimize performance. The trench design offers large cell packing density for reduced channel resistance. The trench design, however, can incur lower blocking capability near the bottom corners of the trenches due to high peak electric fields. The trench design has a large MOS accumulation region and associated capacitance with difficulty to apply field oxide type layers in the trench for miller capacitance reduction. Therefore, the device can possess diminished controllability and high switching losses. Furthermore, the high cell densities in trench designs can result in high short circuit currents.
In “Trench emitter IGBT with lateral and vertical MOS channels” (Proc. 23rd Internat. Conf. on Microelectronics (MIEL 2002), 163-166) an IGBT is described, which includes trench gate electrodes and planar gate electrodes in one device. However, due to the full application of the planar and trench gate design (e.g., i.e. channels are formable between emitter electrode and drift layer at the trench gate electrode as well as at the planar gate electrode), challenges of the planar and trench gate designs are still present in the combined design device.